a. Field of the Invention
The present invention concerns a push-pull amplifier, and more particularly it pertains to a biasing arrangement for a push-pull amplifier employing FET's as the power amplifying elements in its power amplifying stage.
B. Description of the Prior Art
Description will hereunder be made on a known typical biasing arrangement for a push-pull amplifier by referring to FIG. 1. In this drawing, the respective source electrodes of FET's Q3 and Q4 of the power amplifying stage 1 are connected in common to be grounded via a load RL. The drain electrodes of these FET's are connected to positive and negative first power sources +EC1 and -EC1, respectively. The emitter circuit of a transistor Tr1 of the drive stage 2 is connected to a negative second power source -EC2. Also, the collector circuit of said transistor Tr1 is connected to a positive second power source +EC2 is a biasing circuit 3 and a resistor R1. This biasing circuit 3 includes a transistor Tr2 which is connected in series between the resistor R1 and the transistor Tr1. To the base of this transistor Tr2 is applied, as the base bias voltage, a voltage which is obtained by dividing the collector-emitter voltage E.sub.B of said transistor Tr2 by a series connection of resistors R2 and R3. Said collector-emitter voltage E.sub.B of this transistor Tr2 is intended to be applied, as the gate bias voltages, to said FET's Q3 and Q4. And this gate bias voltage is one which needs to be held constant against the variation in the ambient temperature. In the biasing circuit 3 of such circuit arrangement as described above, it should be understood that, when the base-emitter voltage of the transistor Tr2 fluctuates due to the variation of the ambient temperature, the collector-emitter voltage of the transistor Tr1, i.e. the bias voltage E.sub.B for the FET's Q3 and Q4, will undergo fluctuations accordingly. Symbol C1 represents a capacitor intended for "ac" short-circuiting the transistor Tr2.
Also, as the FET's Q3 and Q4, there are used, in general, power FET's having a triode-like non-saturation characteristic. Such an FET, however, is of a nature such that its drain current varies whenever its drain-source voltage fluctuates. In other words, any fluctuation of the output voltages of said first power sources +EC1 and -EC1 will bring about an equivalent fluctuation of the gate bias voltage E.sub.B of the FET's Q3 and Q4. As a result, the operating points of these FET's Q3 and Q4 are caused to fluctuate. Such problems, however, can not be solved by the biasing circuit arrangement of the prior art which has been discussed above.